Practical Digital Design

Bruce Reidenbach has almost forty years of professional experience designing custom digital integrated circuits and FPGAs for military ground and satellite communication systems. His early experience used the paper and pencil logic diagram design process. He transitioned to designing exclusively in VHDL in 1994. He retired from full-time engineering in 2018 and currently teaches an introductory VHDL class at Purdue University Fort Wayne. He continues to perform contract FPGA design services, primarily in the area of underwater sensor systems for use by the US Navy. He received his bachelor's degree in electrical engineering from Purdue University in 1982, and a master's in business administration from Indiana University Fort Wayne in 1989. In his spare time, the author is a long-time volunteer on-air jazz program host on his local public radio station.

PREFACE ACKNOWLEDGMENTS ABOUT THE AUTHOR CHAPTER 1 INTRODUCTION CHAPTER 2 SIGNALS, TIME, AND THE SIMULATION CYCLE CHAPTER 3 THE VHDL DESIGN ENVIRONMENT CHAPTER 4 DECLARATIONS CHAPTER 5 LIBRARIES AND DESIGN UNITS CHAPTER 6 CONCURRENT STATEMENTS CHAPTER 7 SEQUENTIAL STATEMENTS CHAPTER 8 THE PROCESS STATEMENT CHAPTER 9 MODELING CASE STUDIES CHAPTER 10 SUBPROGRAMS CHAPTER 11 SIMULATION AND TEST BENCHES CHAPTER 12 TEST BENCH DEVELOPMENT CHAPTER 13 TEST BENCH CASE STUDIES CHAPTER 14 LOGIC SYNTHESIS CHAPTER 15 ASIC AND FPGA TECHNOLOGY CHAPTER 16 SYNTHESIS CODE EXAMPLES CHAPTER 17 SPECIALIZED CODE EXAMPLES CHAPTER 18 STATE MACHINES CHAPTER 19 FUNCTIONAL DECOMPOSITION CHAPTER 20 FILTER DESIGN EXAMPLE CHAPTER 21 DESIGN REUSE APPENDIX A CODING STYLE GUIDELINES APPENDIX B FUNCTIONAL DESCRIPTION EXAMPLE APPENDIX C VHDL RESERVED WORDS STATEMENT INDEX SUBJECT INDEX